devices incorporated lsh32 32-bit cascadable barrel shifter special arithmetic functions 08/16/2000Clds.32-q 1 configured such that any contiguous 16-bit field (including wraparound of the 32 inputs) may be presented to the output pins under control of the shift code field (wrap mode). alterna- tively, the wrap feature may be disabled, resulting in zero or sign bit fill, as appropriate (fill mode). the shift code control assignments and the resulting input to output mapping for the wrap mode are shown in table 1. essentially the lsh32 is configured as a left shift device. that is, a shift code of 00000 2 results in no shift of the input field. a code of 00001 2 provides an effective left shift of 1 position, etc. when viewed as a right shift, the shift code corresponds to the twos com- plement of the shift distance, i.e., a shift code of 11111 2 (C1 10 ) results in a right shift of one position, etc. when not in the wrap mode, the lsh32 fills bit positions for which there is no corresponding input bit. the fill value and the positions filled depend on the right/left (r/l) direction pin. this pin is a dont care input when in wrap mode. for left shifts in fill mode, lower bits are filled with zero as shown in table 2. for right shifts, however, the sign input is used as the fill value. table 3 depicts the bits to be filled as a function of shift code for the right shift case. note that the r/l input changes only the fill convention, and does not affect the definition of the shift code. in fill mode, as in wrap mode, the shift code input represents the number of shift positions directly for left shifts, but the twos complement of the shift code results in the equivalent right shift. however, for fill mode the r/l input can be viewed as the most q q q q q 32-bit input, 32-bit output multi- plexed to 16 lines q q q q q full 0-31 position barrel shift capability q q q q q integral priority encoder for 32-bit floating point normalization q q q q q sign-magnitude or twos comple- ment mantissa representation q q q q q 32-bit linear shifts with sign or zero fill q q q q q independent priority encoder outputs for block floating point q q q q q 68-pin plcc, j-lead features description lsh32 32-bit cascadable barrel shifter devices incorporated the lsh32 is a 32-bit high speed shifter designed for use in floating point normalization, word pack/ unpack, field extraction, and similar applications. it has 32 data inputs, and 16 output lines. any shift configuration of the 32 inputs, includ- ing circular (barrel) shifting, left shifts with zero fill, and right shift with sign extend are possible. in addition, a built-in priority encoder is provided to aid floating point normalization. shift array the 32 inputs to the lsh32 are applied to a 32-bit shift array. the 32 outputs of this array are multiplexed down to 16 lines for presentation at the device outputs. the array may be lsh32 b lock d iagram 16 oe ms/ls 32-bit barrel shift array 16 16 2:1 32:5 priority encode 32 5 32 sign i 31 -i 0 norm right/left fill/wrap 5 2:1 y 15 -y 0 so 4 -so 0 si 4 -si 0
devices incorporated lsh32 32-bit cascadable barrel shifter special arithmetic functions 08/16/2000Clds.32-q ffs2 significant bit of a 6-bit twos comple- ment shift code, comprised of r/l concatenated with the si 4 Csi 0 lines. thus a positive shift code (r/l = 0) results in a left shift of 0C31 positions, and a negative code (r/l = 1) a right shift of up to 32 positions. the lsh32 can thus effectively select any contigu- ous 32-bit field out of a (sign extended and zero filled) 96-bit "input." output multiplexer the shift array outputs are applied to a 2:1 multiplexer controlled by the ms/ls select line. this multiplexer makes available at the output pins either the most significant or least significant 16 outputs of the shift array. priority encoder the 32-bit input bus drives a priority encoder which is used to determine the first significant position for purposes of normalization. the priority encoder produces a five-bit code representing the location of the first non-zero bit in the input word. code assignment is such that the priority encoder output represents the number of shift positions required to left align the first non-zero bit of the input word. prior to the priority encoder, the input bits are individu- ally exclusive ored with the sign input. this allows normalization in floating point systems using twos complement mantissa representation. a negative value in twos complement representation will cause the exclusive or gates to invert the input data to the encoder. as a result the leading significant digit will always be "1." this affects only the encoder inputs; the shift array always operates on the raw input data. the priority encoder function table is shown in table 4. t able 1. w rap m ode s hift c ode d efinitions shift code shift code shift code shift code shift code y y y y y 31 31 31 31 31 y y y y y 30 30 30 30 30 y y y y y 29 29 29 29 29 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? y y y y y 16 16 16 16 16 y y y y y 15 15 15 15 15 ? ? ? y y y y y 2 2 2 2 2 y y y y y 1 1 1 1 1 y y y y y 0 0 0 0 0 00000 i 31 i 30 i 29 ? ? ? i 16 i 15 ? ? ? i 2 i 1 i 0 00001 i 30 i 29 i 28 ? ? ? i 15 i 14 ? ? ? i 1 i 0 i 31 00010 i 29 i 28 i 27 ? ? ? i 14 i 13 ? ? ? i 0 i 31 i 30 00011 i 28 i 27 i 26 ? ? ? i 13 i 12 ? ? ? i 31 i 30 i 29 ? ???? ? ?? ?? ? ???? ? ???? ? ?? ?? ? ???? ? ???? ? ?? ?? ? ???? 01111 i 16 i 15 i 14 ? ? ? i 1 i 0? ? ? i 19 i 18 i 17 10000 i 15 i 14 i 13 ? ? ? i 0 i 31 ? ? ? i 18 i 17 i 16 10001 i 14 i 13 i 12 ? ? ? i 31 i 30 ? ? ? i 17 i 16 i 15 10010 i 13 i 12 i 11 ? ? ? i 30 i 29 ? ? ? i 16 i 15 i 14 ? ???? ? ?? ?? ? ???? ? ???? ? ?? ?? ? ???? ? ???? ? ?? ?? ? ???? 11100 i 3 i 2 i 1? ? ? i 20 i 19 ? ? ? i 6 i 5 i 4 11101 i 2 i 1 i 0? ? ? i 19 i 18 ? ? ? i 5 i 4 i 3 11110 i 1 i 0 i 31 ? ? ? i 18 i 17 ? ? ? i 4 i 3 i 2 11111 i 0 i 31 i 30 ? ? ? i 17 i 16 ? ? ? i 3 i 2 i 1 t able 2. f ill m ode s hift c ode d efinitions l eft s hift shift code shift code shift code shift code shift code y y y y y 31 31 31 31 31 y y y y y 30 30 30 30 30 y y y y y 29 29 29 29 29 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? y y y y y 16 16 16 16 16 y y y y y 15 15 15 15 15 ? ? ? y y y y y 2 2 2 2 2 y y y y y 1 1 1 1 1 y y y y y 0 0 0 0 0 00000 i 31 i 30 i 29 ? ? ? i 16 i 15 ? ? ? i 2 i 1 i 0 00001 i 30 i 29 i 28 ? ? ? i 15 i 14 ? ? ? i 1 i 0 0 00010 i 29 i 28 i 27 ? ? ? i 14 i 13 ? ? ? i 0 00 00011 i 28 i 27 i 26 ? ? ? i 13 i 12 ? ? ? 000 ? ???? ? ?? ?? ? ???? ? ???? ? ?? ?? ? ???? ? ???? ? ?? ?? ? ???? 01111 i 16 i 15 i 14 ? ? ? i 1 i 0? ? ? 000 10000 i 15 i 14 i 13 ? ? ? i 0 0 ? ? ? 000 10001 i 14 i 13 i 12 ? ? ? 00 ? ? ? 000 10010 i 13 i 12 i 11 ? ? ? 00 ? ? ? 000 ? ???? ? ?? ?? ? ???? ? ???? ? ?? ?? ? ???? ? ???? ? ?? ?? ? ???? 11100 i 3 i 2 i 1? ? ? 00 ? ? ? 000 11101 i 2 i 1 i 0? ? ? 00 ? ? ? 000 11110 i 1 i 0 0 ? ? ? 00 ? ? ? 000 11111 i 0 00 ? ? ? 00 ? ? ? 000
devices incorporated lsh32 32-bit cascadable barrel shifter special arithmetic functions 08/16/2000Clds.32-q 3 normalize multiplxer the norm input, when asserted results in the priority encoder output driving the internal shift code inputs directly. it is exactly equivalent to routing the so 4 Cso 0 outputs back to the si 4 Csi 0 inputs. the norm input provides faster normalization of 32-bit data by avoiding the delay associated with routing the shift code off chip. when using the norm function, the lsh32 should be placed in fill mode, with the r/l input low. applications examples normalization of mantissas up to 32 bits can be accomplished directly by a single lsh32. the norm input is asserted, and fill mode and left shift are selected. the normalized mantissa is then available at the device output in two 16-bit segments, under the control of the output data multiplexer select, the ms/ls. if it is desirable to avoid the necessity of multiplexing output data in 16-bit segments, two lsh32 devices can be used in parallel. both devices receive the same input word, with the ms/ls select line of one wired high, and the other low. each device will then independently determine the shift distance required for normalization, and the full 32 bits of output data will be available simultaneously. t able 3. f ill m ode s hift c ode d efinitions r ight s hift t able 4. p riority e ncoder f unction t able i i i i i 31 31 31 31 31 i i i i i 30 30 30 30 30 i i i i i 29 29 29 29 29 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i i i i i 16 16 16 16 16 i i i i i 15 15 15 15 15 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i i i i i 2 2 2 2 2 i i i i i 1 1 1 1 1 i i i i i 0 0 0 0 0 shift code shift code shift code shift code shift code 1xx ? ? ? xx ? ? ? x x x 00000 01x ? ? ? xx ? ? ? x x x 00001 001 ? ? ? xx ? ? ? x x x 00010 ???? ? ?? ?? ? ???? ? ???? ? ?? ?? ? ???? ? 000 ? ? ? 1x ? ? ? x x x 01111 000 ? ? ? 01 ? ? ? x x x 10000 000 ? ? ? 00 ? ? ? x x x 10001 ???? ? ?? ?? ? ???? ? ???? ? ?? ?? ? ???? ? 000 ? ? ? 00 ? ? ? 0 1 x 11110 000 ? ? ? 00 ? ? ? 0 0 1 11111 000 ? ? ? 00 ? ? ? 0 0 0 11111 shift code shift code shift code shift code shift code y y y y y 31 31 31 31 31 y y y y y 30 30 30 30 30 y y y y y 29 29 29 29 29 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? y y y y y 16 16 16 16 16 y y y y y 15 15 15 15 15 ? ? ? y y y y y 2 2 2 2 2 y y y y y 1 1 1 1 1 y y y y y 0 0 0 0 0 00000 s s s ? ? ? ss ? ? ? sss 00001 s s s ? ? ? ss ? ? ? ssi 31 00010 s s s ? ? ? ss ? ? ? si 31 i 30 00011 s s s ? ? ? ss ? ? ? i 31 i 30 i 29 ? ???? ? ?? ?? ? ???? ? ???? ? ?? ?? ? ???? ? ???? ? ?? ?? ? ???? 01111 s s s ? ? ? ss ? ? ? i 19 i 18 i 17 10000 s s s ? ? ? si 31 ? ? ? i 18 i 17 i 16 10001 s s s ? ? ? i 31 i 30 ? ? ? i 17 i 16 i 15 10010 s s s ? ? ? i 30 i 29 ? ? ? i 16 i 15 i 14 ? ???? ? ?? ?? ? ???? ? ???? ? ?? ?? ? ???? ? ???? ? ?? ?? ? ???? 11100 s s s ? ? ? i 20 i 19 ? ? ? i 6 i 5 i 4 11101 s s s ? ? ? i 19 i 18 ? ? ? i 5 i 4 i 3 11110 s s i 31 ? ? ? i 18 i 17 ? ? ? i 4 i 3 i 2 11111 s i 31 i 30 ? ? ? i 17 i 16 ? ? ? i 3 i 2 i 1
devices incorporated lsh32 32-bit cascadable barrel shifter special arithmetic functions 08/16/2000Clds.32-q ffs4 long-word normalization (multiple cycles) normalization of floating point mantissas longer than 32 bits can be accomplished by cascading lsh32 units. when cascading for normaliza- tion, the device inputs are overlapped such that each device lower in priority than the first shares 16 inputs with its more significant neighbor. fill mode and left shift are selected, however, internal normalization (norm) is not used. the most significant result half of each device is enabled to the output. the shift out (so 4 Cso 0 ) lines of the most significant slice are connected to the shift in lines of all clock normalization requiring shifts longer than 16 bits can be accom- plished by a bank-select technique described below. single cycle long-word normalization an extension of the above concept is a single clock normalization of long words (potentially requiring shifts of more than 15 places). the arrange- ment of lsh32s required is shown in figure 1. cascading of lsh32 units is accomplished by connecting the si 3 C si 0 input lines of each unit to the so 3 C so 0 outputs of the most significant device in the row as before. essen- slices, including the first. the excep- tion is that all si 4 lines are grounded, limiting the shift distance to 16 positions. the shift distance required for normalization is produced by the priority encoder in the most signifi- cant slice. the priority encoder will produce the shift code necessary to normalize the input word if the leading non-zero digit is found in the upper 16 bits. if this is the case, the number of shift positions necessary to accomplish normalization is placed on the so 4 Cso 0 outputs for use by all slices, and the appropriate 0C15 bit shift is accomplished. if the upper 16 bits are all zero, then the maximum shift of 15 places is executed. single f igure 1. s ingle c ycle l ong -w ord n ormalization u sing lsh32 s lsh32 si 3-0 5 so 4-0 oe 4 lsh32 5 oe 4 lsh32 5 oe 4 lsh32 5 oe 4 si 4 lsh32 oe 4 lsh32 oe 4 lsh32 oe 4 lsh32 oe 4 lsh32 oe 4 lsh32 oe 4 si 4 si 4 i 63 -i 48 y 63 -y 48 msbs priority encode 2:4 decode i 47 -i 32 i 31 -i 16 i 15 -i 0 0 i 47 -i 32 i 31 -i 16 i 15 -i 0 0 i 31 -i 16 i 15 -i 0 0 i 16 -i 0 0 si 3-0 si 3-0 si 3-0 so 4-0 si 3-0 si 3-0 si 3-0 si 3-0 so 4-0 si 3-0 si 4 si 3-0 so 4-0 y 47 -y 32 y 31 -y 16 y 15 -y 0
devices incorporated lsh32 32-bit cascadable barrel shifter special arithmetic functions 08/16/2000Clds.32-q 5 tially the lsh32s are arranged in multiple rows or banks such that the inputs to successive rows are left- shifted by 16 positions. the outputs of each row are multiplexed onto a three-state bus. the normalization problem then reduces to selecting from among the several banks that one which has the first non-zero bit of the input value among its 16 most significant positions. if the most significant one in the input file was within the upper 16 locations of a given bank, the so 4 output of the most significant slice in that bank will be low. single clock normalization can thus be accomplished simply by enabling onto the three-state output bus the highest priority bank in which this condition is met. in this way the input word will be normalized regardless of the number of shift positions required to accomplish this. the number of shift positions can be determined simply by concatenation of the so 3 Cso 0 outputs of the most significant slice in the selected row with the encoded output enable-bits determining the row number. note that lower rows need not be fully populated. this is because they represent left shifts in multiples of 16 positions, and the lower bits of the output word will be zero filled. in order to accomplish this zero fill, the least significant device in each row is always enabled, and the row select is instead connected to the si 4 input. this will force the shift length of the least significant device to a value greater than 15 whenever the row containing that device is not selected. this results in zero fill being accom- plished by the equivalently positioned slice in a higher bank, as shown in the diagram. block floating point with a small amount of external logic, block floating point operations are easily accomplished by the lsh32. data resulting from a vector operation are applied to the lsh32 with the norm-input deasserted. the so 4 C so 0 outputs fill then represent the normalization shift distance for each vector element in turn. by use of an external latch and comparator, the maximum shift distance encountered across all elements in the vector is saved for use in the next block opera- tion (or block normalization). during this subsequent pass through the data, the shift code saved from the previous pass is applied uniformly across all elements of the vector. since the lsh32 is not used in the internal normalize mode, this operation can be pipelined, thereby obtaining the desired shift distance for the next pass while simultaneously applying the normalization required from the previous pass.
devices incorporated lsh32 32-bit cascadable barrel shifter special arithmetic functions 08/16/2000Clds.32-q ffs6 symbol parameter test condition min typ max unit v oh output high voltage v cc = min., i oh = C2.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 v v ih input high voltage 2.0 v cc v v il input low voltage (note 3) 0.0 0.8 v i ix input current ground v in v cc (note 12) 20 a i oz output leakage current ground v out v cc (note 12) 20 a i cc1 v cc current, dynamic (notes 5, 6) 10 30 ma i cc2 v cc current, quiescent (note 7) 1.5 ma storage temperature ........................................................................................................... C65c to +150c operating ambient temperature ........................................................................................... C55c to +125c v cc supply voltage with respect to ground ............................................................................ C0.5 v to +7. 0v input signal with respect to ground ........................................................................................ C3. 0 v to +7.0 v signal applied to high impedance output ............................................................................... C3.0 v to +7.0 v output current into low outputs ................................................................................................ ............. 25 ma latchup current ................................................................................................................ ............... > 400 ma m aximum r atings above which useful life may be impaired (notes 1, 2, 3, 8) o perating c onditions to meet specified electrical and switching characteristics e lectrical c haracteristics over operating conditions (note 4) mode temperature range (ambient) supply voltage active operation, commercial 0c to +70c 4.75 v v cc 5.25 v active operation, military C55c to +125c 4.50 v v cc 5.50 v
devices incorporated lsh32 32-bit cascadable barrel shifter special arithmetic functions 08/16/2000Clds.32-q 7 1234567890123456 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1234567890123456 1234567890123456789012345678901212345678901234 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1234567890123456789012345678901212345678901234 lsh32C 42 * 32 20 symbol parameter min max min max min max t iy i, sign inputs to y outputs 42 32 20 t iyn i, sign inputs to y outputs, normalize mode 75 60 20 t iso i, sign inputs to so outputs 55 42 20 t siy si, right/left to y outputs 52 40 20 t msy ms/ls select to y outputs 28 24 15 t dis three-state output disable delay (note 11) 20 20 15 t ena three-state output enable delay (note 11) 20 20 15 switching characteristics c ommercial o perating r ange (0c to +70c) notes 9, 10 (ns) lsh32C 50 * 40 * 30 * symbol parameter min max min max min max t iy i, sign inputs to y outputs 50 40 30 t iyn i, sign inputs to y outputs, normalize mode 85 75 58 t iso i, sign inputs to so outputs 65 52 42 t siy si, right/left to y outputs 62 52 40 t msy ms/ls select to y outputs 32 26 24 t dis three-state output disable delay (note 11) 22 20 17 t ena three-state output enable delay (note 11) 22 20 17 m ilitary o perating r ange (C55c to +125c) notes 9, 10 (ns) 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 *d iscontinued s peed g rade high impedance sign t ena t dis ms/ls oe t msy t siy t iy, t iyn t iso si 4 -si 0 right/left i 31 -i 0 so 4 -so 0 y 31 -y 0 y 31 -y 0 s witching w aveforms
devices incorporated lsh32 32-bit cascadable barrel shifter special arithmetic functions 08/16/2000Clds.32-q ffs8 1. maximum ratings indicate stress specifications only. functional oper- ation of these products at values beyond those indicated in the operating condi- tions table is not implied. exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. the products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. neverthe- less, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. this device provides hard clamping of transient undershoot and overshoot. in- put levels below ground or above v cc will be clamped beginning at C0.6 v and v cc + 0.6 v. the device can withstand indefinite operation with inputs in the range of C0.5 v to +7.0 v. device opera- tion will not be adversely affected, how- ever, input current levels will be well in excess of 100 ma. 4. actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. supply current for a given applica- tion can be accurately approximated by: where n = total number of device outputs c = capacitive load per output v = supply voltage f = clock frequency 6. tested with all outputs changing ev- ery cycle and no load, at a 5 mhz clock rate. 7. tested with all inputs within 0.1 v of v cc or ground, no load. 8. these parameters are guaranteed but not 100% tested. ncv f 4 2 notes 9. ac specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 v (except t dis test), and input levels of nominally 0 to 3.0 v. output loading may be a resistive divider which provides for specified i oh and i ol at an output voltage of v oh min and v ol max respectively. alternatively, a diode bridge with upper and lower current sources of i oh and i ol respectively, and a balancing voltage of 1.5 v may be used. parasitic capacitance is 30 pf minimum, and may be distributed. this device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. as a result, care must be exercised in the testing of this device. the following measures are recommended: a. a 0.1 f ceramic capacitor should be installed between v cc and ground leads as close to the device under test (dut) as possible. similar capacitors should be installed between device v cc and the tester common, and device ground and tester common. b. ground and v cc supply planes must be brought directly to the dut socket or contactor fingers. c. input voltages should be adjusted to compensate for inductive ground and v cc noise to maintain required dut input levels relative to the dut ground pin. 10. each parameter is shown as a min- imum or maximum value. input re- quirements are specified from the point of view of the external system driving the chip. setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. responses from the internal circuitry are specified from the point of view of the device. output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. for the t ena test, the transition is measured to the 1.5 v crossing point with datasheet loads. for the t dis test, the transition is measured to the 200mv level from the measured steady-state output voltage with 10ma loads. the balancing volt- age, v th , is set at 3.5 v for z-to-0 and 0-to-z tests, and set at 0 v for z- to-1 and 1-to-z tests. 12. these parameters are only tested at the high temperature extreme, which is the worst case for leakage current. s1 i oh i ol v th c l dut oe 0.2 v t dis t ena 0.2 v 1.5 v 1.5 v 3.5v vth 1 z 0 z z 1 z 0 1.5 v 1.5 v 0v vth v ol * v oh * v ol * v oh * measured v ol with i oh = C10ma and i ol = 10ma measured v oh with i oh = C10ma and i ol = 10ma f igure b. t hreshold l evels f igure a. o utput l oading c ircuit
devices incorporated lsh32 32-bit cascadable barrel shifter special arithmetic functions 08/16/2000Clds.32-q 9 1234567890123456789012345678901212345678901234567 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1234567890123456789012345678901212345678901234567 discontinued package 68-pin ordering information 68-pin 0c to +70c c ommercial s creening plastic j-lead chip carrier (j2) LSH32JC32 lsh32jc20 speed 32 ns 20 ns ceramic pin grid array (g1) C55c to +125c mil-std-883 c ompliant C55c to +125c c ommercial s creening a b c d e f g h j k l top view through package (i.e., component side pinout) 12345 6 7 8 9 10 11 i 29 i 30 sign so 3 so 1 norm si 3 si 1 r/l y 30/14 y 29/13 i 28 i 27 y 28/12 y 27/11 i 26 i 25 y 26/10 y 25/9 i 24 i 23 y 24/8 y 23/7 i 22 i 21 y 22/6 y 21/5 i 20 i 19 y 20/4 y 19/3 i 18 i 17 y 18/2 y 17/1 i 16 i 15 y 16/0 oe i 14 gnd i 12 i 10 i 8 i 6 i 4 i 2 i 0 v cc ms/ls i 31 so 4 so 2 so 0 si 4 si 2 si 0 f/w y 31/15 gnd i 13 i 11 i 9 i 7 i 5 i 3 i 1 v cc 67 68 64 65 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 3 top view 466 63 62 1 2 27 32 33 34 35 36 37 38 61 39 40 9 41 42 43 5 86 7 28 29 30 31 gnd i 13 i 12 i 11 i 10 i 9 i 8 i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 v cc v cc i 30 i 31 sign so 4 so 3 so 2 so 1 so 0 norm si 4 si 3 si 2 si 1 si 0 r/l f/w y 31/15 i 29 i 28 i 27 i 26 i 25 i 24 i 23 i 22 i 21 i 20 i 19 i 18 i 17 i 16 i 15 i 14 gnd y 30/14 y 29/13 y 28/12 y 27/11 y 26/10 y 25/9 y 24/8 y 23/7 y 22/6 y 21/5 y 20/4 y 19/3 y 18/2 y 17/1 y 16/0 oe ms/ls
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